1. Field of the Invention
The present invention is directed in general to the field of semiconductor devices. In one aspect, the present invention relates to the formation of silicided features in semiconductor devices.
2. Description of the Related Art
The use of silicides is well known in the field of semiconductor fabrication. A silicide is a silicon metal alloy. In MOS (metal oxide semiconductor) fabrication processes, silicides are used to provide low resistivity structures for contacting the gate electrode and the source and drain electrodes of a MOS transistor. Silicides preferably also serve as a barrier layer that prevents interaction between the semiconductor material of the source/drain areas and a subsequently formed interconnect.
Candidate metals for silicide formation that have received significant development effort include the Group VIII metal silicides, such as PtSi, Pd2Si, TiSi2, CoSi2, ErSi2, and NiSi, which exhibit desirably low resistivity, react with silicon at desirably low temperatures, and do not react with most dielectrics. Unfortunately, none of these materials is ideal for all applications in advanced MOS fabrication. For example, the use of nickel as a silicide metal for source/drain regions is problematic because NiSi exhibits NiSi2 related spiking on p+ active regions, and encroachment under the spacer and gate electrode. Cobalt silicide is also problematic when formed in polysilicon gates because of dramatically increased resistance at lateral poly dimensions below 40 nm where agglomeration and voiding occur.
Accordingly, a need exists for a semiconductor manufacturing process which efficiently incorporates the benefits of multiple types of silicides without incurring disadvantages associated with any of the silicides. There is also a need for a fabrication process which avoids performance limitations associated with existing silicide materials at smaller device geometries. In addition, there is a need for extending the usefulness of existing silicide materials to smaller device geometries. There is also a need for improved semiconductor processes and devices to overcome the problems in the art, such as outlined above. Further limitations and disadvantages of conventional processes and technologies will become apparent to one of skill in the art after reviewing the remainder of the present application with reference to the drawings and detailed description which follow.
It will be appreciated that for simplicity and clarity of illustration, elements illustrated in the drawings have not necessarily been drawn to scale. For example, the dimensions of some of the elements are exaggerated relative to other elements for purposes of promoting and improving clarity and understanding. Further, where considered appropriate, reference numerals have been repeated among the drawings to represent corresponding or analogous elements.